In semiconductor fabrication using single and dual damascene methods, a series of interconnect layers are formed by depositing an inter-metal dielectric (IMD) material, forming a trench in the IMD layer, overfilling the trench with copper (to form a conductive trace), and planarizing the substrate. Chemical mechanical polishing (CMP) is commonly used for planarization, to remove all the copper above the surface of the IMD layer.
Uneven topography can reduce yield and affect device performance. The CMP process is intended to achieve a flat topography to improve yield. Nevertheless, during CMP, copper and the adjacent IMD material are removed from the wafer at different rates, creating non-uniform topography. Line density is known to affect the removal rates of the IMD and copper materials. Generally, the topography impact is greater in a dense pattern region than in a low density (“iso”) region. Dishing and erosion are the two most costly topography issues that arise with copper CMP. Dishing occurs when the copper recedes below or protrudes above the level of the adjacent dielectric. Dishing is often observed as a concavity extending across several lines. Erosion is a localized thinning of the dielectric between two adjacent lines.
If the CMP process leaves an uneven topography, then subsequent processing of the substrate may be affected adversely.